CY37256P160-125AI

The main feature of the Ultra37000 CPLD family is its In-System Reprogrammable (ISR) capability, which allows for programming or reprogramming of the device on-board without changing the system timing or device pinout. This feature simplifies design changes during debug or field upgrades, eliminating the need for board respins. The Ultra37000 family implements ISR through a JTAG-compliant interface, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance.

The purpose of the Programmable Interconnect Matrix (PIM) in the Ultra37000 CPLD architecture is to provide a global routing matrix for signals from I/O pins and feedbacks from logic blocks. It allows for robust interconnection to avoid fitting and density limitations, with inputs from all I/O and dedicated input pins, as well as macrocell feedbacks. The PIM outputs signals routed to the appropriate logic blocks, providing 36 inputs to each logic block and their complements for 32-bit operations in a single pass through the device. The PIM also simplifies timing and improves routing capacity within the Ultra37000 family.