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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

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製品の詳細については、「製品仕様」を参照してください。

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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

200 ドル以上のご注文には、限定版の中華風のギフトがプレゼントされます.

200 ドル以上のご注文には、限定版の中華風のギフトがプレゼントされます.

1000 ドルを超える注文は、30 ドルの配送料免除の対象となります.

5000 ドルを超える注文では、配送料と取引手数料が免除されます.

これらのオファーは新規顧客と既存顧客の両方に適用され、2024 年 1 月 1 日から 2024 年 12 月 31 日まで有効です。.

  • メーカー:

    TI

  • データシート:

    ISO7220CDR datasheet

  • パッケージ/ケース:

    SOP-8

  • 製品カテゴリ:

    ICチップ

  • RoHS Status: RoHS ステータス Lead free/RoHS Compliant

今すぐ見積もりリクエストを送信してください。3 日以内に見積もりを提出する予定です。 4月 26, 2024。 今すぐご注文ください。以内に取引が完了する予定です。 5月 01, 2024。 追伸:時間はGMT+8:00に従います。

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ストック:15000 PCS

当社では、12 時間以内に迅速な見積もりを提供することをお約束します。さらにサポートが必要な場合は、下記までお問い合わせください。 sales@censtry.com.

ISO7220CDR 製品詳細

FEATURES

• 1, 25, and 150-Mbps Signaling Rate Options

– Low Channel-to-Channel Output Skew; 1 ns max

– Low Pulse-Width Distortion (PWD); 1 ns max

– Low Jitter Content; 1 ns Typ at 150 Mbps

• Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 19) 

• 4000-Vpeak Isolation, 560 V peak VIORM

– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1

– 50 kV/μs Typical Transient Immunity

• Operates with 3.3-V or 5-V Supplies

• 4 kV ESD Protection

• High Electromagnetic Immunity

• –40°C to 125°C Operating Range


APPLICATIONS

• Industrial Fieldbus

– Modbus

– Profibus™ – DeviceNet™ Data Buses

• Computer Peripheral Interface

• Servo Control Interface

• Data Acquisition


DESCRIPTION

The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The small capacitance and resulting time constant provide very fast operation with signaling rates available from 0 Mbps (DC) to 150 Mbps.(1)The A- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter and the additional propagation delay.

These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS.

These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.

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