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Ask for advice on the voltage at both ends of the PMOS switch circuit.

Hardware design
10月 23, 2020 by Fisher 468

As shown in the figure, it is found in the actual test that when the G poles of the two tubes are low, the D pole outputs 3.3V voltage normally. When the G poles of the two tubes are at high level, the D pole of Q1 will have a voltage output of 1V, and the D pole of Q2 will have a 0.4V output. I beg you to analyze

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Fredrick ポストする October 23, 2020

If the voltage of GS pole is not discharged, a resistor should be added.

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Linnea ポストする October 23, 2020

What is the MCU control signal voltage? Is it 5V or 3.3V? Look at the MOS specification. It says that the minimum VGS(th) is -0.5. Is there a problem with the difference between the control voltage and the source voltage, causing micro-conduction? You change the MCU control voltage and try it. Where is the problem?

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Freyja ポストする October 23, 2020

It may be the leakage current of the MOS tube.

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