AT17C256-10PI

The user can select the polarity of the reset function for the AT17 Series FPGA Configuration EEPROMS by programming a special EEPROM bit. This special feature allows the user to choose between RESET/OE or RESET /OE as the reset polarity option.

The purpose of the ATSeries FPGA Configuration EEPROMS (Configurator) is to provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. It is designed to establish the I/O and logic functions of the FPGA and their associated interconnections through a configuration program loaded either automatically upon power up or on command, depending on the state of the FPGA mode pins. The EEPROMs are also compatible with Master Serial Mode for automatic loading of the configuration program from an external memory. Additionally, for multiple FPGAs configured as a daisy-chain or for future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory. The AT17 Series can be programmed with industry standard programmers.

The ATSeries FPGA Configuration EEPROMS are available in two different pin configurations: 8-pin DIP and 20-pin PLCC and SOIC.