DP83867ISRGZR

1 Features

• Extra Low Latency TX < 90ns, RX < 290ns

• Power consumption 457mW

• Exceeds 8kV IEC 61000-4-2 ESD Protection

• Meets EN55011 Class B Emission Standards

• 16 Programmable RGMII Delay Modes on RX/TX

• Integrated MDI Termination Resistors

• Programmable MAC Interface Termination impedance

• WoL (Wake on LAN) Packet Detection

• 25-MHz or 125-MHz Synchronized Clock Output

• IEEE 1588 Time Stamp Support

• RJ45 Mirror Mode

• Fully Compatible to IEEE 802.3 10BASE-Te,

100BASE-TX, and 1000BASE-T specification

• Cable Diagnostics

• RGMII and SGMII MAC Interface Options

• Configurable I/O Voltage (3.3V, 2.5V, 1.8V)

• Fast Link up / Link Drop Modes

• JTAG Support

2 Applications

• Motor and Motion Control

• Industrial Factory Automation

• Industrial Embedded Computing

• Wired and Wireless Communications Infrastructure

• Test and Measurement

• Consumer Electronics

3 Description

The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8kV IEC 61000-4-2 (direct contact).

The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII).

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.

Designed for low power, the DP83867 consumes only 457mW under full operating power. Wake on LAN can be used to lower system power consumption.

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