TCAN1043GDMTRQ1

The TCAN1043xx-Q1 transceivers are typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. These applications usually include power management technology that allows for power to be gated to the application via an enable (EN) or inhibit (INH) pin. A single 5V regulator can be used to drive both VCC and VIO, or independent 5V and 3.3V regulators can be used to drive VCC and VIO separately. The bus termination is shown for illustrative purposes. In addition, the TCAN1043xx-Q1 transceivers are typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. The device provides CAN transceiver differential transmit capability to the bus and differential receive capability. It meets or exceeds the specifications of the ISO 11898-2 (2016) High-Speed CAN physical layer standard and has been certified to the requirements of ISO11898-2/5 according to the GIFT/ICT High-Speed CAN test specification. Therefore, the TCAN1043xx-Q1 transceiver is intended to be used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol.

The TCAN1043xx-Q1 transceiver provides several protection features, including: - IEC ESD protection up to ±8kV - Bus fault protection: ±58V (non-H variants) and ±70V (H variants) - Undervoltage protection on supply terminals - TXD Dominant Time Out (DTO) - Thermal shutdown protection - Receiver common mode input voltage: ±30V These features ensure the safe and reliable operation of the transceiver in various applications.

The typical loop delay of the TCAN1043xx-Q1 transceiver mentioned in the document is not explicitly stated in the search results. Sorry, I couldn't find the answer in the PDF.