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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

200 ドル以上のご注文には、限定版の中華風のギフトがプレゼントされます.

200 ドル以上のご注文には、限定版の中華風のギフトがプレゼントされます.

1000 ドルを超える注文は、30 ドルの配送料免除の対象となります.

5000 ドルを超える注文では、配送料と取引手数料が免除されます.

これらのオファーは新規顧客と既存顧客の両方に適用され、2024 年 1 月 1 日から 2024 年 12 月 31 日まで有効です。.

  • メーカー:

    TI

  • データシート:

    TLC555QDR datasheet

  • パッケージ/ケース:

    SOP-8

  • 製品カテゴリ:

    ICチップ

  • RoHS Status: RoHS ステータス Lead free/RoHS Compliant

今すぐ見積もりリクエストを送信してください。3 日以内に見積もりを提出する予定です。 5月 03, 2024。 今すぐご注文ください。以内に取引が完了する予定です。 5月 08, 2024。 追伸:時間はGMT+8:00に従います。

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ストック:65000 PCS

当社では、12 時間以内に迅速な見積もりを提供することをお約束します。さらにサポートが必要な場合は、下記までお問い合わせください。 sales@censtry.com.

TLC555QDR 製品詳細



  • Very Low Power Consumption

− 1 mW Typ at VDD = 5 V

  • Capable of Operation in Astable Mode

  • CMOS Output Capable of Swinging Rail to Rail

  • High Output-Current Capability

    − Sink 100 mA Typ

    − Source 10 mA Typ

  • Output Fully Compatible With CMOS, TTL,and MOS

  • Low Supply Current Reduces Spikes

  • During Output Transitions

  • Single-Supply Operation From 2 V to 15 V

  • Functionally Interchangeable With the

  • NE555; Has Same Pinout

  • ESD Protection Exceeds 2000 V Per

  • MIL-STD-883C, Method 3015.2

  • Available in Q-Temp Automotive 

  • High Reliability Automotive Applications

    Configuration Control/Print Support

    Qualification to Automotive Standards

description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.


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