TSB12LV31

Features

The TSB12LV31 supports the following features:

• Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus (1394)†

• Fully Interoperable with FireWire Implementation of 1394

• Compatible with Texas Instruments TSB11LV01 and TSB21LV03 Physical Layer Controllers (Phys)

• Single 3.3-V supply operation with 5-V Tolerant Capabilities using 5-V Bias Terminals

• High-performance 100-Pin PZ (S–PQFP–G100) package.

• Programmable Microcontroller Interface with 8-Bit or 16-Bit Data Bus, Three Modes of Operation, and Clock Frequency to 50 Mhz

• 50-quadlet (200-Byte) FIFO Accessed Through Microcontroller Interface Supports Asynchronous and Isochronous Operations

• Programmable FIFO Size For Asynchronous Transmit FIFO and General-Receive FIFO

• Single-Channel Support for Isochronous Transmit from Unbuffered 8-Bit Isochronous Port (IsoPort)

• Isochronous Receive to FIFO or to Unbuffered 8-Bit IsoPort

• Isochronous Header Synchronous-Bit Detection on Receive

• Automatically Reports IRM NODE_ID and Verifies Automatic 1394 Self-ID

• Transfer Rates of 100 Mbits/s and 200 Mbits/s

• Asynchronous Packet Reception to Internal FIFO (Accessed Through the Microcontroller Interface)

• Asynchronous Packet Transmission from Internal FIFO (Accessed Through the Microcontroller Interface)

• Generation of External Microcontroller Clock from SCLK (SCLK/4)

• Generation of 32-Bit Cyclic Redundancy Check (CRC) for Transmission of 1394 Packets

• 32-Bit CRC Checking on Reception of 1394 Packets

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